Journal
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
Volume 20, Issue 1, Pages 14-20Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TASC.2009.2034471
Keywords
Access time; high-speed measurement; hybrid memory; interface circuit
Funding
- Office of Naval Research [N00014-03-1-0065]
- VLSI Design and Education Center (VDEC)
- University of Tokyo, Tokyo, Japan
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A 64-kb subnanosecond Josephson-CMOS hybrid random-access memory (RAM) has been developed with ultra-fast hybrid interface circuits. The hybrid memory is designed and fabricated using a commercial 0.18-mu m CMOS process and NEC-SRL's 2.5-kA/cm(2) Nb process for Josephson circuits. The millivolt-level Josephson signals are amplified to volt-level CMOS digital signals by a hybrid interface amplifier, which is the most challenging part of the memory system. The performance of this amplifier is optimized by minimizing its parasitic capacitance loading. The 4-K operation of short-channel CMOS devices and circuits is reviewed, and a complete 4-K CMOS BSIM3 model, which has been verified by experiments, is discussed. The memory bit-line output currents are detected by ultralow-power high-speed Josephson devices. Here, we report the first high-frequency access-time measurements on the full critical path showing 600 ps for a single bit. We discuss future designs made to reduce the crosstalk and improve margins, as well as plans to reduce power dissipation and latency.
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