Journal
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
Volume 19, Issue 3, Pages 149-153Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TASC.2009.2019195
Keywords
ADC; high voltage driver; MCM; multi-J(c); multi-rate; SERDES; superconductor integrated circuits
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Many applications of superconductor integrated circuits may require a small part of the circuit to work at the highest possible clock frequency, e. g. an ADC in the receiver front-end, while more complex parts of the circuits may work at a lower frequency, e. g. a digital filter. Since the maximum clock frequency is proportional to the square root of the Josephson critical current density (J(c)), such circuits can be realized as multi-J(c) circuits containing trilayers with different J(c)'s. A fabrication technology will be presented enabling a single chip to accommodate circuits optimized for different critical current densities. Details of the multi-J(c) process will be discussed as well as the typical circuit implementations and test results.
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