Journal
IEEE PHOTONICS TECHNOLOGY LETTERS
Volume 22, Issue 8, Pages 544-546Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LPT.2010.2041445
Keywords
Complementary metal-oxide-semiconductor (CMOS) integrated circuits; design automation; optical device fabrication; optical planar waveguide components
Funding
- Defense Advanced Research Project Agency
- National Science Foundation
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A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs in three foundry scaled-CMOS processes from two semiconductor manufacturers.
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