4.6 Article Proceedings Paper

A 1.2 nJ/bit 2.4 GHz Receiver With a Sliding-IF Phase-to-Digital Converter for Wireless Personal/Body Area Networks

Journal

IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 49, Issue 12, Pages 3005-3017

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2014.2365092

Keywords

Bluetooth low energy receiver; Delta-Sigma frequency-to-digital converter; Delta-Sigma phase-to-digital converter; frequency demodulator; frequency digitizer; phase demodulator; phase digitizer; PLL demodulator; ultra-low power receiver; ZigBee receivers

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This paper presents an ultra-low power 2.4 GHz FSK/PSK RX for wireless personal/body area networks. A single-channel phase-tracking RX based on a sliding-IF phase-to-digital conversion (SIF-PDC) loop is proposed to directly demodulate and digitize the frequency/phase-modulated information. The sliding-IF frequency plan reduces the power consumption of the multi-phase LO generation. A phase rotator is adopted in SIF-PDC to guarantee frequency stability, i.e., avoid the frequency pulling by interference or frequency drift. It equivalently transforms the RF signal processing from the I/Q amplitude domain to a digital-phase domain, which saves up to nearly 40% on power consumption and relaxes the digital baseband complexity. A phase-domain linear model of the proposed SIF-PDC is presented to analyze the frequency response. Fabricated in a 90 nm CMOS technology, the presented RX consumes 2.4 mW at 2Mbps data rate, i.e., 1.2 nJ/b efficiency, and achieves a sensitivity of -92 dBm.

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