Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 49, Issue 12, Pages 2846-2856Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2014.2362851
Keywords
ADC; analog-to-digital converter; background timing skew calibration; SAR ADC; subrange SAR ADC; successive approximation register ADC; time-interleaved ADC; timing skew calibration; timing skew
Categories
Funding
- MIT Center for Integrated Circuits and Systems (CICS)
- Samsung Fellowship
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This paper presents a time-interleaved (TI) SAR ADC which enables background timing skew calibration without a separate timing reference channel and enhances the conversion speed of each SAR channel. The proposed ADC incorporates a flash ADC operating at the full sampling rate of the TI ADC. The flash ADC output is multiplexed to resolve MSBs of the SAR channels. Because the full-speed flash ADC does not suffer from timing skew errors, the flash ADC output is also used as a timing reference to estimate the timing skew of the TI SAR ADCs. A prototype ADC is designed and fabricated in a 65 nm CMOS process. After background timing skew calibration, 51.4 dB SNDR, 59.1 dB SFDR, and +/- 1.0 LSB INL/DNL are achieved at 1 GS/s with a Nyquist rate input signal. The power consumption is 18.9 mW from a 1.0 V supply, which corresponds to 62.3 fJ/step FoM.
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