Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 48, Issue 12, Pages 3049-3058Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2013.2279571
Keywords
ADC; alternate comparators; analog-to-digital converter; asynchronous; constant common mode; offset compensation; redundant; SAR; successive approximation
Categories
Ask authors/readers for more resources
An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step. High-speed operation is achieved by converting each sample with two alternate comparators clocked asynchronously and a redundant capacitive DAC with constant common mode to improve the accuracy of the comparator. A low-power, clocked capacitive reference buffer is used, and fractional reference voltages are provided to reduce the number of unit capacitors in the capacitive DAC (CDAC). The ADC stacks the CDAC with the reference capacitor to reduce the area and enhance the settling speed. Background calibration of comparator offset is implemented. The ADC consumes 3.1 mW from a 1 V supply and occupies 0.0015 mm(2).
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available