Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 48, Issue 2, Pages 516-526Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2012.2217892
Keywords
Asynchronous pipeline; digital background calibration; time amplifier; time-to-digital converter (TDC)
Categories
Funding
- IT R&D program of MKE/KEIT [10039159]
- NRF [2012-0000625]
- IDEC of Korea
- Korea Evaluation Institute of Industrial Technology (KEIT) [10039159] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
- National Research Foundation of Korea [2008-0062617] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
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This paper presents an asynchronous pipelined all-digital 10-b time-to-digital converter (TDC) with fine resolution, good linearity, and high throughput. Using a 1.5-b/stage pipeline architecture, an on-chip digital background calibration is implemented to correct residue subtraction error in the seven MSB stages. An asynchronous clocking scheme realizes pipeline operation for higher throughput. The TDC was implemented in standard 0.13-mu m CMOS technology and has a maximum throughput of 300 MS/s and a resolution of 1.76 ps with a total conversion range of 1.8 ns. The measured DNL and INL were 0.6 LSB and 1.9 LSB, respectively.
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