4.6 Article Proceedings Paper

A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V

Journal

IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 47, Issue 10, Pages 2534-2545

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2012.2206683

Keywords

Low power; process variations; ultra low power; voltage reference; 2 transistor voltage reference

Funding

  1. National Science Foundation
  2. Direct For Computer & Info Scie & Enginr [910851] Funding Source: National Science Foundation
  3. Division Of Computer and Network Systems [910851] Funding Source: National Science Foundation

Ask authors/readers for more resources

Sensing systems such as biomedical implants, infrastructure monitoring systems, and military surveillance units are constrained to consume only picowatts to nanowatts in standby and active mode, respectively. This tight power budget places ultra-low power demands on all building blocks in the systems. This work proposes a voltage reference for use in such ultra-low power systems, referred to as the 2T voltage reference, which has been demonstrated in silicon across three CMOS technologies. Prototype chips in 0.13 mu m show a temperature coefficient of 16.9 ppm/degrees C (best) and line sensitivity of 0.033%/V, while consuming 2.22 pW in 1350 mu m(2). The lowest functional V is 0.5 V. The proposed design improves energy efficiency by 2 to 3 orders of magnitude while exhibiting better line sensitivity and temperature coefficient in less area, compared to other nanowatt voltage references. For process spread analysis, 49 dies are measured across two runs, showing the design exhibits comparable spreads in TC and output voltage to existing voltage references in the literature. Digital trimming is demonstrated, and assisted one temperature point digital trimming, guided by initial samples with two temperature point trimming, enables TC < 50 ppm/degrees C and +/- 0.35% output precision across all 25 dies. Ease of technology portability is demonstrated with silicon measurement results in 65 nm, 0.13 mu m, and 0.18 mu m CMOS technologies.

Authors

I am an author on this paper
Click your name to claim this paper and add it to your profile.

Reviews

Primary Rating

4.6
Not enough ratings

Secondary Ratings

Novelty
-
Significance
-
Scientific rigor
-
Rate this paper

Recommended

No Data Available
No Data Available