Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 47, Issue 7, Pages 1693-1702Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2012.2191684
Keywords
Photonics; interconnect; monolithic integration; SOI; high-speed I/O; many-core; multi-core; sense-amplifiers; transimpedance amplifiers; integrating receivers; chip-to-chip links
Categories
Funding
- DARPA
- NSF
- FCRP IFC
- Trusted Foundry
- Intel
- MIT CICS
- APIC
- Santec
- NSERC
- Div Of Electrical, Commun & Cyber Sys
- Directorate For Engineering [0844994] Funding Source: National Science Foundation
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Integrated photonics has emerged as an I/O technology that can meet the throughput demands of future many-core processors. Taking advantage of the low capacitance environment provided by monolithic integration, we developed an integrating receiver front-end built directly into a clocked comparator, achieving high sensitivity and energy-efficiency. A simple model of the receiver provides intuition on the effects of wiring and photodiode capacitance, and leads to a photodiode-splitting technique enabling improved sensitivity at higher data rates. The receiver is characterized in situ and shown to operate with A-sensitivity at 3.5 Gb/s with a power consumption of 180 W ( 52 fJ/bit) and area of 108 m. This work demonstrates that photonics and electronics can be jointly integrated in a standard 45-nm SOI process.
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