Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 47, Issue 1, Pages 272-283Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2011.2164298
Keywords
CMOS image sensor (CIS); column-parallel folding integration/cyclic ADC; high resolution and high dynamic range (DR); low noise; multiple sampling technique
Categories
Funding
- Ministry of Education, Culture, Sports, Science and Technology
- Knowledge Cluster Initiative
- Grants-in-Aid for Scientific Research [22246049] Funding Source: KAKEN
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A low temporal noise and high dynamic range CMOS image sensor is developed. A 1Mpixel CMOS image sensor with column-parallel folding-integration and cyclic ADCs has 80 mu V-rms (1.2e(-)) temporal noise, 82 dB dynamic range using 64 samplings in the folding-integration ADC mode. Very high variable gray-scale resolution of 13b through 19b is attained by changing the number of samplings of pixel outputs. The implemented CMOS image sensor using a 0.18-mu m technology has the sensitivity of 10-V/lx . s, the conversion gain of 67-mu V/e(-), and linear digital code range of more than 4 decades.
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