A 90-nm CMOS Threshold-Compensated RF Energy Harvester

This paper presents an efficient energy harvester for RF-powered sensor networks. The circuit is based on an improved multi-stage rectifier, which exploits a fully passive threshold self-compensation scheme to overcome the limitation due to the input dead zone. A CAD-oriented design methodology is also proposed, which is aimed at maximizing the overall power conversion efficiency of the harvester through an optimum trade-off among matching losses, power reflection and rectifier efficiency. According to the proposed methodology, a 915-MHz harvester comprising an integrated input matching network and a 17-stage self-compensated rectifier has been designed and fabricated in a 90-nm CMOS technology. The rectifier exhibits a remarkably low input power threshold, as it is able to deliver a 1-V dc output voltage to a capacitive load with a very small input power of -24 dBm (4 mu W). When driving a 1-M Omega load, the device can supply a 1.2-V output with an input power of -18.8 dBm (13.1 mu W). The achieved results exceed the performance of previously reported RF multi-stage rectifiers in standard analog CMOS technology.