Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 45, Issue 4, Pages 751-758Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2010.2042253
Keywords
Charge pumps; multi-phase; voltage doubler; Vmin; Vccmin
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A multi-phase 1 GHz charge pump in 32 nm logic process demonstrates a compact area (159 x 42 mu m(2)) for boosting supply voltage from twice the threshold voltage (2Vth) to 3-4Vth. Self contained clocking with metal-finger flying capacitors enable embedding voltage boost functionality in close proximity to digital logic for supplying low current Vmin requirement of state elements in logic blocks. Multi-phase operation with phase separation of the order of buffer delays avoids the need for a large storage reservoir capacitor. Special configuration of the pump stages to work in parallel enables a fast (5 ns) output transition from disable to enable state. The multi-phase pump operated as a 1 V to 2 V doubler with > 5 mA output capability addresses the need for a gated power delivery solution for logic blocks having state-preservation Vmin requirements.
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