Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 44, Issue 12, Pages 3285-3293Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2009.2032624
Keywords
CMOS; current-steering; D/A converters; digital-to-analog converter (DAC); full Nyquist; HD3; high frequency; high speed; IM3
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A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 < -60 dBc beyond 1 GHz while driving a 50 Omega load with an output swing of 2.5V(ppd) and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with always-ON biasing.
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