Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 44, Issue 12, Pages 3314-3328Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2009.2032637
Keywords
ADC; calibration; digital; mixed signal
Categories
Ask authors/readers for more resources
This paper presents a pipelined ADC with two fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity and DAC noise cancellation (DNC) to compensate for DAC capacitor mismatches. It is the first IC implementation of HDC, and the results demonstrate that HDC and DNC together facilitate low-voltage operation and enable reductions in power dissipation relative to comparable conventional state-of-the-art pipelined ADCs. The pipelined ADC achieves a peak SNR of 70 dB and a -1 dBFS SFDR of 85 dB at a sample-rate of 100 MHz. It is implemented in a 90 nm CMOS process and consumes 130 mW from 1.2 V and 1.0 V analog and digital power supplies, respectively.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available