Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 43, Issue 1, Pages 150-162Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2007.908001
Keywords
charge pump; data endurance; data retention; diode-switch; MOS-switch; phase-change memory; phase change random access memory (PRAM); SEG technology; slow-quench; write-verify
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A 512 Mb diode-switch PRAM has been developed in a 90 nm CMOS technology. The vertical diode-switch using the SEG technology has achieved minimum cell size and disturbance-free core operation. A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are proposed. The 512 Mb PRAM has achieved read throughput of 266 MB/s through the proposed schemes. The write throughput was 0.54 MB/s in internal x2 write mode, and increased to 4.64 MB/s with x16 accelerated write mode at 1.8 V supply.
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