Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 43, Issue 4, Pages 929-937Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2008.917559
Keywords
flash memory; floating gate coupling effect; multilevel cell; NAND flash memory
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A 16 Gb 16-level-cell (16LC) NAND Hash memory using 70 nm Design Rule has been developed [1]. This 16LC NAND Hash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow V-th distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.
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