4.6 Article Proceedings Paper

Terahertz CMOS Frequency Generator Using Linear Superposition Technique

Journal

IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 43, Issue 12, Pages 2730-2738

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2008.2004868

Keywords

CMOS Terahertz generator; DAC-to-RF conversion efficiency; fundamental-to-fourth harmonic signal conversion ratio; linear superposition (LS) circuit technique; phase noise of terahertz CMOS signal generation; terahertz signal generation

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A low Terahertz (324 GHz) frequency generator is realized in 90 nm CMOS by linearly superimposing quadruple (N = 4) phase shifted fundamental signals at one fourth of the output frequency (81 GHz). The developed technique minimizes the fundamental, second and third order harmonics without extra filtering and results in a high fundamental-to-4 th harmonic signal conversion ratio of 0.17 or - 15.4 dB. The demonstrated prototype produces a calibrated -46 dBm output power when biased at 1 V and 12 mA with 4 GHz tuning range and extrapolated phase noise of -91 dBc/Hz at 10 MHz frequency offset. The linear superposition (LS) technique can be generalized for all even number cases (N = 2k, where k = 1, 2, 3, 4, ... , n) with different tradeoffs in output power and frequency. As CMOS continues to scale, we anticipate the LS N = 4 VCO to generate signals beyond 2 Terahertz by using 22 nm CMOS and produce output power up to -1.5 dBm with 1.7% power added efficiency with an LS VCO + Class-B Power Amplifier cascaded circuit architecture.

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