Journal
IEEE ELECTRON DEVICE LETTERS
Volume 35, Issue 5, Pages 521-523Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2014.2313332
Keywords
Digital etch; InGaAs; MOSFET; nanowire; reactive ion etching; top-down; vertical channel
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Funding
- NSF Center for Energy Efficient Electronics Science NSF [0939514]
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This letter introduces a novel inductively coupled plasma-reactive ion etching (ICP-RIE) technique based on a BCl3/SiCl4/Ar chemistry for fabricating sub-20 nm diameter InGaAs nanowires with smooth, vertical sidewall and high aspect ratio (>10). To mitigate dry-etch damage, RIE is followed by a digital etch method comprised of multiple cycles of self-limiting low power O-2 plasma oxidation and diluted H2SO4 rinse. Using these technologies, we demonstrate vertical InGaAs gate-all-around nanowire MOSFETs with 30 nm diameter. Digital etch improves both the subthreshold swing and peak transconductance, indicating enhanced sidewall interfacial quality. The combination of RIE and digital etch techniques proposed here is promising for future 3-D III-V MOSFETs.
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