Journal
IEEE ELECTRON DEVICE LETTERS
Volume 35, Issue 1, Pages 141-143Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2013.2290555
Keywords
Silicon nanowire; reconfigurable transistor; RFET; inverter; logic gates; transient simulations
Categories
Funding
- Deutsche Forschungsgemeinschaft in the framework of the Project ReproNano [MI 1247/6-1]
- Cluster of Excellence CfAED
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A feasibility and performance study of electrically reconfigurable nanowire transistors with selectable pFET and nFET operations is presented. The challenges toward circuit implementation are evaluated based on transient simulations of logic circuits. A novel physical structure capable of computing a NAND as well as NOR function is introduced. The new approach provides a flexible platform to develop and test fine-grain reconfigurable circuits and systems.
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