Journal
IEEE ELECTRON DEVICE LETTERS
Volume 35, Issue 3, Pages 357-359Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2014.2301800
Keywords
In-Ga-Zn-O (IGZO); ZnO trap layer; oxide semiconductor; charge trap memory; top gate structure
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Funding
- National Research Foundation of Korea through the Korean Government [2012011730]
- Ministry of Science, ICT and Future Planning, Korea, in the ICT Research and Development Program
- Korea Communications Agency (KCA) [R0101-14-0133] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
- National Research Foundation of Korea [22A20130000119, 2012R1A2A2A02011730] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
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We proposed a charge-trap-type memory transistor with a top-gate structure composed of Al2O3 blocking/ZnO charge-trap/IGZO active/Al2O3 tunneling layer. The memory ON/OFF ratio higher than six-orders-of magnitude was obtained after the programming when the width and amplitude of program pulses were 100 ms and +/- 20 V, respectively. Excellent endurance was successfully confirmed under the repetitive programming with 10(4) cycles. The memory ON/OFF ratio higher than 10(3) was guaranteed even after the lapse of 10(4) s. Interestingly, the retention properties were affected by the bias conditions for read-out operations.
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