Journal
IEEE ELECTRON DEVICE LETTERS
Volume 34, Issue 10, Pages 1289-1291Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2013.2275182
Keywords
High-k dielectric stacks; interfacial layer; reliability; soft breakdown; thermo-chemical model; time-dependent dielectric breakdown (TDDB)
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Funding
- SUTD Research Grant [SRG ASPE 2010 004]
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We use the thermo-chemical model of bond breakage to investigate the degradation occurring in dual-layer SiOx/HfSiON gate dielectric stacks during low-compliance soft breakdown (BD) experiments, with the ultimate goal of identifying the first layer that degrades. Time-dependent dielectric breakdown experiments reveal that the degradation of conventional SiON and SiOx/HfSiON dielectric stacks have the same kinetics, i.e., activation energy and field acceleration factor. This finding, supported by physics-based BD simulations, shows that the degradation in SiOx/HFSiON stacks is governed by the defect generation in the silicon oxide interfacial layer, which is the first that degrades in the multilayer stack.
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