Journal
IEEE ELECTRON DEVICE LETTERS
Volume 32, Issue 4, Pages 521-523Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2011.2107498
Keywords
Accumulation mode; gate all around (GAA); inversion mode (IM); nanowire (NW); thin-film transistor (TFT)
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Funding
- National Science Council of the Republic of China [NSC 99-2811-M-009-007]
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In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.
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