Journal
IEEE ELECTRON DEVICE LETTERS
Volume 32, Issue 4, Pages 440-442Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2011.2106150
Keywords
FinFETs; interface traps; thermionic theory
Categories
Funding
- FOM
- European Community [214989-AFSiD]
- Semiconductor Research Corporation
- Focus Center Research Program Center for Materials, Structures, and Devices
- National Science Foundation
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The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultrascaled FinFET geometries where the presence of a few traps can strongly influence the device behavior. Typical methods for interface trap density (D-it) measurements are not performed on ultimate devices but on custom-designed structures. We present the first set of methods that allow direct estimation of D-it in state-of-the-art FinFETs, addressing a critical industry need.
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