Interface Trap Density Metrology of State-of-the-Art Undoped Si n-FinFETs

The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultrascaled FinFET geometries where the presence of a few traps can strongly influence the device behavior. Typical methods for interface trap density (D-it) measurements are not performed on ultimate devices but on custom-designed structures. We present the first set of methods that allow direct estimation of D-it in state-of-the-art FinFETs, addressing a critical industry need.