Design of Tunneling Field-Effect Transistors Based on Staggered Heterojunctions for Ultralow-Power Applications

This letter presents the design of a tunneling FET with III-V-based tunnel heterojunctions for operation in digital circuits with supply voltages as low as 0.3 V. A representative implementation is predicted to achieve an ON-state current drive of 0.4 mA/mu m with an OFF-state current of 50 nA/mu m. Comparison with homojunction counterparts reveals that the hetero-tunnel-junction implementations may address better the design tradeoff between ON-state drive and OFF-state leakage.