4.6 Article

Organic-Transistor-Based Nano-Floating-Gate Memory Devices Having Multistack Charge-Trapping Layers

Journal

IEEE ELECTRON DEVICE LETTERS
Volume 31, Issue 5, Pages 503-505

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2010.2041743

Keywords

Gold nanoparticles; nonvolatile memory; organic memory; pentacene

Funding

  1. World Gold Council [RP05-08]
  2. National Research Foundation of Korea (NRF)/MEST [R11-2005-048-00000-0]
  3. Korean Ministry of Knowledge Economy
  4. Korean government (MEST) [313-2008-2-D00597, 2008-0059952, 2009-0077593]
  5. National Research Foundation of Korea [2009-0077593, 2008-0060669, 2008-0059952] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)

Ask authors/readers for more resources

Nano-floating-gate memory devices having multistack charge-trapping layers are developed. Controlled gold nanoparticles encapsulated with polyelectrolytes are used as charge-trapping elements. Programmable memory characteristics are observed according to the programming/erasing operations in pentacene-based organic-transistor memory devices. The memory window can be increased effectively by the adoption of multistack charge-trapping layers. The data-retention measurement shows that the programmed/erased states are maintained relatively well according to the time elapsed. This letter is based on simple solution processes at low temperature, so it has a potential use in fabricating nano-floating-gate memory devices on plastic substrates.

Authors

I am an author on this paper
Click your name to claim this paper and add it to your profile.

Reviews

Primary Rating

4.6
Not enough ratings

Secondary Ratings

Novelty
-
Significance
-
Scientific rigor
-
Rate this paper

Recommended

No Data Available
No Data Available