Journal
IEEE ELECTRON DEVICE LETTERS
Volume 30, Issue 2, Pages 158-160Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2008.2009362
Keywords
Bilayer; graphene; nanoelectronics; tunneling
Categories
Funding
- SRC NRI SWAN center
- Texas Emerging Technology Fund
Ask authors/readers for more resources
We propose a new type of graphene-based transistor intended to allow lower voltage, lower power operation than possible with Complementary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors. Increased energy efficiency is not only important for its own sake, but is also necessary to allow continued device scaling and the resulting increase in computational power in CMOS-like logic circuits. We describe the basic device structure and physics and predicted current-voltage characteristics.. Advantages over CMOS in terms of lower voltage and power are discussed.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available