Vertical silicon-nanowire formation and gate-all-around MOSFET

This letter presents a, vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50: 1) vertical nanowires with diameter similar to 20 nm are achieved from lithography and dry-etch. defined Si-pillars with subsequent oxidation, The surrounding gate length is controlled using etch back of the sacrificial oxide. N-MOS devices thus fabricated with gate length similar to 150 nm showed excellent transistor characteristics with large drive current (1.0 X 10(3) mu A/mu m), high I-on/I-off ratio (similar to 10(7)), good subthreshold slope (similar to 80 mV/dec) and low drain-induced barrier lowering (similar to 10 mV/V). Along with good electrical characteristics, the use of low cost bulk wafers, and simple gate definition process steps could make this device a suitable candidate for next generation technology nodes.