Journal
IEEE ELECTRON DEVICE LETTERS
Volume 29, Issue 5, Pages 518-521Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2008.920267
Keywords
gate-all-around (GAA); nanowire (NW); nonvolatile memory (NVM); silicon-oxide-nitride-oxide-silicon (SONOS)
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This letter presents a high-speed silicon-oxidenitride-oxide-silicon (SONOS) nonvolatile memory cell in gate-all-around Si-nanowire (NW) architecture, which is fabricated by using a top-down process technology. The NW cell exhibits faster program and erase (P/E) speed compared to the corresponding Planar device; 1 mu s for programming and I ms for erasing at V-GS = +/- 11 V with a threshold voltage shift Delta V-TH of 2.6 V using the Fowler-Nordheim tunneling mechanism. At these P/E conditions, the planar device does not show appreciable change. The improvement is originated from: 1) increased electric field at the Si-SiO2 interface; 2) reduced effective tunnel barrier width; and 3) low electric field in the blocking oxide, as analyzed through simulation. In addition, good data retention makes the NW-based SONOS cell a potential candidate for future high-speed low-voltage NAND-type nonvolatile Flash memory applications.
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