Journal
IBM JOURNAL OF RESEARCH AND DEVELOPMENT
Volume 52, Issue 6, Pages 583-597Publisher
IBM CORP
DOI: 10.1147/JRD.2008.5388565
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Funding
- IBM Microelectronics Research Laboratory
- Central Scientific Services
- EV Group and Suss MicroTec
- DARPA [N66001-00-C-8003, N66001-04-C-8032]
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An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.
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