4.7 Article

Scaling of pneumatic digital logic circuits

Journal

LAB ON A CHIP
Volume 15, Issue 5, Pages 1360-1365

Publisher

ROYAL SOC CHEMISTRY
DOI: 10.1039/c4lc01048e

Keywords

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Funding

  1. National Science Foundation [ECCS-1102397]
  2. Defense Advanced Research Projects Agency (DARPA) N/MEMS S&T Fundamentals Program [N66001-1-4003]
  3. NSF IGERT [0549479]
  4. Direct For Education and Human Resources [0549479] Funding Source: National Science Foundation
  5. Directorate For Engineering [1102397] Funding Source: National Science Foundation
  6. Division Of Graduate Education [0549479] Funding Source: National Science Foundation
  7. Div Of Electrical, Commun & Cyber Sys [1102397] Funding Source: National Science Foundation

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The scaling of integrated circuits to smaller dimensions is critical for achieving increased system complexity and speed. Digital logic circuits composed of pneumatic microfluidic components have to this point been limited to a circuit density of 2-4 gates cm(-2), constraining the complexity of the digital systems that can be achieved. We explored the use of precision machining techniques to reduce the size of pneumatic valves and resistors, and to achieve more accurate and efficient placement of ports and vias. In this way, we attained an order of magnitude increase in circuit density, reaching as high as 36 gates cm(-2). A 12-bit binary counter circuit composed of 96 gates was realized in an area of 360 mm(2). The reduction in size also brought an order of magnitude increase in speed. The frequency of a 13-stage ring oscillator increased from 2.6 Hz to 22.1 Hz, and the maximum clock frequency of a binary counter increased from 1/3 Hz to 6 Hz.

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